Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering

Director, Center for Advanced Electronics through Machine Learning (CAEML)

Professor, Coordinated Science Laboratory

email: elyse AT illinois DOT edu

Mailing address:

Current Research Interests:

- Machine learning methods for electronics modeling and design optimization
- ESD-robust high-speed I/O circuit design
- Compact modeling
- System-level ESD reliability
- Soft error mitigation
- Transient latch-up
- CDM-ESD protection for System-in-Package and System-on-Chip
- Efficient simulation of IC CDM reliability
- Gate dielectric reliability

Why a focus on ESD?

Electrostatic discharge can direct several amperes of current into a nano-scale integrated circuit (IC) whose transistors are designed to carry only micro- or milli- amperes of current. Thermal breakdown will occur almost instantly if the current is not shunted away from the transistors. We strive to create protection devices which are compatible with the semiconductor process and that turn on rapidly, so as to safely shunt the ESD current away from the fragile transistors. It can be challenging to ensure that the protection devices do not compromise the normal operation of the circuit, which makes the concept of self-protecting circuits attractive. Given the high cost of fabricating chips in a modern process and the increasing design time, it is desired that an IC passes qualification testing -- re: functionality and reliability - on the first silicon spin. This requires that the component be simulated prior to fabrication. Tools and models for simulating reliability are less mature than those used to verify timing, analog functionality, etc. Models created for the protection devices and the ESD sources need to strike a balance between physical rigor and computational efficiency. If a chip experiences ESD while it is operating (e.g. if a user rubs her smart-phone with a cloth to remove fingerprints), the protection circuit may prevent physical damage to the part, but noise will be injected into the IC. Supply noise in particular can cause widespread problems. The origin of the ESD-induced supply noise has commonalities with simultaneous switching noise and it's possible the two will have a common solution.

We focus on ESD because it is a serious, pervasive and unavoidable reliability hazard and because it lets us solve challenging problems at the intersection of semiconductor devices and IC design.

Courses Taught:

- ECE 441 - Solid State Electronic Devices
- ECE 442 - Electronic Circuits
- ECE 482 - Large Scale Integrated Circuit Design
- ECE 585 - Characterization, Design and Modeling of CMOS Devices

Biography:

Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She received the B.S. degree (with distinction) from Cornell University, the M.S. degree from Stanford University, and the Ph.D. degree from University of California, Berkeley in 1992, all in electrical engineering. From 1984 through 1987, she was a Member of Technical Staff at AT&T Bell Laboratories in Holmdel, NJ. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a joint project of the University of Illinois, Georgia Tech and North Carolina State University.

Dr. Rosenbaum has authored or co-authored nearly 200 technical papers; she has been an editor for *IEEE Transactions on Device and Materials Reliability* and *IEEE Transactions on Electron Devices. *She is serving as the General Chair for the 2018 IEEE International Reliability Physics Symposium. She was the recipient of a Best Student Paper Award from the IEDM, Outstanding and Best Paper Awards from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and the ESD Association’s Industry Pioneer Recognition Award. She is a Fellow of the IEEE.

Prospective Students:

I supervise graduate student researchers, and I welcome inquiries from prospective students with relevant experience and strong academic records. On occasion, I will also agree to supervise an undergraduate researcher; this opportunity is restricted to students enrolled at UIUC and is generally done in the context of senior thesis research. I am not able to sponsor students from international universities for summer internships and will not respond to email requests for such sponsorship.

Publications:

Y. Xiu, S. Sagan, A. Battini, X. Ma, M. Raginsky and E. Rosenbaum, "Stochastic modeling of air electrostatic discharge parameters," to appear 2018 IEEE Int. Reliability Physics Symp. (March 2018).

M.-S. Keel and E. Rosenbaum, "ESD self-protection of high-speed transceivers using adaptive active bias conditioning," IEEE Trans. Device and Materials Rel., vol. 17, no. 1, pp. 113-120, 2017.

N. Thomson, Y. Xiu and E. Rosenbaum, "Soft-failures induced by system-level ESD," IEEE Trans. Device Materials Rel., vol. 17, no. 1, pp. 90-98, 2017.

Y. Lin, M.-S. Keel, A. Faust, A. Xu, N. Shanbhag, E. Rosenbaum and A. Singer, "A study of a BER-optimal ADC-based receiver for serial links," IEEE Trans. Circuits and Syst. I, vol. 63, no. 5, pp. 693-704, 2017.

Z. Liu, M. Raginsky and E. Rosenbaum,"Verilog-A compatible recurrent neutral network model for transient circuit simulation," in IEEE Conf. Elec. Performance of Electronic Packaging and Systems, 2017.

N. Thomson, C. Reiman, Y. Xiu and E. Rosenbaum, "On-chip monitors of supply-noise generated by system-level ESD," in 2017 EOS/ESD Symp. Proc.

Y. Xiu, N. Thomson, R. Mertens, C. Reiman and E. Rosenbaum, "Chip-level ESD-induced noise on internally and externally regulated power supplies," in 2017 EOS/ESD Symp Proc.

M.-S. Keel and E. Rosenbaum, “CDM-reliable T-coil techniques for a 25-Gb/s wireline receiver front-end,” IEEE Trans. Device and Materials Rel., vol. 16, no. 4, pp. 513-520, 2016. (Invited)

K.-H. Meng, V. Shukla and E. Rosenbaum, "Full component modeling and simulation of charged device model ESD," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 7, pp. 1105-1113, 2016.

R. Mertens and E. Rosenbaum, “Physical basis for CMOS SCR compact models,” IEEE Transactions on Electron Devices, vol. 63, no. 1, pp. 296–302, Jan. 2016.

Y. Xiu, R. Mertens, N. Thomson and E. Rosenbaum, "Experimental study of supply voltage stability during ESD," in Proc. IEEE Int. Reliability Physics Symposium, pp. 6A6.1-6A6.6, 2016.

Y. Xiu, A. Appaswamy, Z. Chen, A. Salman, M. Dissegna, G. Boselli and E. Rosenbaum, "Improving the long pulse width failure current of NPN in BiCMOS technology,"in Proc. IEEE Int. Reliability Physics Symposium, pp. EL5.1-EL5.4, 2016.

S. Vora, R. Jiang, S. Vasudevan and E. Rosenbaum, "Application level investigation of system-level ESD-induced soft failures," in 2016 EOS/ESD Symp. Proc.

Y. Xiu, F. Farbiz, A. Salman, Y. Zu, M. Dissegna, G. Boselli, and E. Rosenbaum, "Case study of DPI robustness of a MOS-SCR structure for automotive applications," in 2016 EOS/ESD Symp. Proc.

V. Shukla and E. Rosenbaum, "Charge device model reliability of three-dimensional integrated circuits," IEEE Trans. Device and Materials Reliability, vol. 15, no. 4, Dec. 2015.

R. Mertens, N. Thomson, Y. Xiu, and E. Rosenbaum, “Analysis of active-clamp response to power-on ESD: Power supply integrity and performance tradeoffs,” IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 263–271, Sept. 2015. (Invited Paper)

C. Reiman, N. Thomson, Y. Xiu, R. Mertens, and E. Rosenbaum, “Practical methodology for the extraction of SEED models,” Proc. 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 2B.1–2B.10, 2015.

Y. Xiu, N. Thomson, R. Mertens, and E. Rosenbaum, “S-parameter based modeling of system-level ESD test bed,” Proc. 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 7B.1–7B.10, 2015.

K.-H. Meng, R. Mertens, and E. Rosenbaum, “Piecewise-linear model with transient relaxation for circuit-level ESD simulation,” IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 464–466, Sept. 2015.

M.-S. Keel and E. Rosenbaum, "CDM-reliable T-coil techniques for high-speed wireline receivers," 2015 EOS/ESD Symp.

E. Rosenbaum, K.-H. Meng, Y. Xiu and N. Thomson, "Current challenges in component-level and system-level ESD simulation," Asia-Pacific EMC Symposium, May 2015.

Z. Chen, R. Mertens C. Reiman and E. Rosenbaum, “Improved GGSCR layout for overshoot reduction,” 2015 Int. Reliability Physics Symp.

V. Shukla, G. Boselli, M. Dissegna, C. Duvvury, R. Sankaralingam and E. Rosenbaum, "Pre-silicon prediction of charged device model peak discharge current of microelectronic components," IEEE. Trans. Dev. Materials Rel., vol. 14, no. 3, pp. 801-809, 2014. (Invited Paper)

K-H Meng, A. Gerdemann, J. Miller and E. Rosenbaum, "A co-optimization methodology on ESD robustness and functionality for pad-ring circuitry," EOS/ESD Symp. Proc.,. pp. 232-241, 2014.

R. Mertens, N. Thomson, Y. Xiu and E. Rosenbaum, "Theory of active clamp response to power-on ESD and implications for power supply integrity," EOS/ESD Symp. Proc., pp. 242-251, 2014.

N. Thomson, Y. Xiu, R. Mertens, M-S Keel and E. Rosenbaum, "Custom Test Chip for System-level ESD Investigations," EOS/ESD Symp. Proc., pp. 92-101, 2014.

Y. Xiu, N. Thomson, R. Mertens and E. Rosenbaum, "A mechanism for logic upset induced by power-on ESD," EOS/ESD Symp. Proc., pp. 161-170, 2014.

K-H Meng and E. Rosenbaum, "Verification of snapback model by transient I-V measurement for circuit simulation of ESD response," IEEE Trans. Dev. Materials Rel., vol. 13, no. 2, pp. 371-378, 2013. (Invited Paper)

N. Jack and E. Rosenbaum, "Comparison of FICDM and Wafer-level CDM test methods," IEEE. Trans. Dev. Materials Rel., vol. 13, no. 2, pp. 379-387, 2013. (Invited Paper)

R. Mertens and E. Rosenbaum, "A physics-based compact model for SCR devices used in ESD protection circuits," Proc. IEEE Int. Rel. Phys. Symp., pp. 2B.2.1-2B.2.7, 2013.

R. Mertens and E. Rosenbaum, "Separating SCR and trigger circuit related overshoot in SCR-based ESD protection circuits," EOS/ESD Symp. Proc., pp. 125-132, 2013.

K.-H. Meng and E. Rosenbaum, "Layout-aware, distributed, compact model for multi-finger MOSFETs operating under ESD conditions," EOS/ESD Symp. Proc., pp. 97-104, 2013.

M-S Keel, N. Jack and E. Rosenbaum "ESD-resilient active biasing scheme for high-speed SSTL I/Os," EOS/ESD Symp. Proc., pp. 63-70, 2013.

V. Shukla, G. Boselli, M. Dissegna, C. Duvvury, R. Sankaralingam and E. Rosenbaum, "Predictive modeling of peak discharge current during charged device model test of microelectronic components," EOS/ESD Symp. Proc., pp. 383-390, 2013.

S. Ruth, J. Miller, A. Gerdemann, M. Stockinger, M. Etherton, M. Moosa, A. Dobbin, R. Mertens, E. Rosenbaum, P. Colombo, M. Cordoni, N. Guitard, "Investigation of product burn-in failures due to powered NPN bipolar latching of active MOSFET rail clamps," EOS/ESD Symp. Proc., pp. 313-322, 2013.

N. Jack and E. Rosenbaum, "Comparing FICDM and wafer-level CDM test methods: apples to oranges?" EOS/ESD Symp. Proc., pp. 231-239, 2012.

K-H Meng and E. Rosenbaum,"The need for transient I-V measurement of device ESD response," EOS/ESD Symp. Proc., pp. 290-297, 2012.

R. Mertens, H. Kunz, A. Salman, G. Boselli and E. Rosenbaum, "A flexible simulation model for system level ESD stresses with applications to ESD design and troubleshooting," EOS/ESD Symp. Proc., pp. 373-378, 2012.

W-Y Chen, E. Rosenbaum, and M-D Ker, "Diode-triggered silicon controlled rectifier with reduced voltage overshoot for CDM ESD protection," IEEE Trans. Dev. Materials Rel., vol. 12, no. 1, pp. 10-14, 2012.

E. Rosenbaum, V. Shukla and M-S Keel, "ESD protection networks for 3D integrated circuits," in Proc. IEEE Int. 3D System Integration Conference, 2011.

A. Kripanidhi and E. Rosenbaum, "Layout sensitivities of transient external latchup," in Proc. IEEE Int. Reliability Physics Symp., 2012.

N. Thomson, N. Jack and E. Rosenbaum, " Exponential-edge transmission line pulsing for snap-back device characterization," in Proc. IEEE Int. Reliabilty Physics Symp., 2012.

F. Farbiz and E. Rosenbaum, "Modeling and understanding of external latchup in CMOS technologies-part I: modeling latchup trigger current," IEEE Trans. Dev. Materials Rel., vol. 11, no. 3, pp. 417-425, 2011.

F. Farbiz and E. Rosenbaum, "Modeling and understanding of external latchup in CMOS technologies-part II: minority carrier collection efficiency," IEEE Trans. Dev. Materials Rel., vol. 11, no. 3, pp. 426-432, 2011.

N. Jack, V. Shukla and E. Rosenbaum, "Comparison of wafer-level with package-level CDM stress facilitated by real-time probing," IEEE Trans. Device Materials Rel., vol. 11, no. 4, pp. 522-530, 2011. (Invited paper)

N. Olson, N. Jack, V. Shukla and E. Rosenbaum, "CDM-ESD induced damage in components using stacked-die packaging," Proc. IEEE Custom Integrated Circuits Conf., pp. 6-4.1-6-4.4, 2011.

A. Faust and E. Rosenbaum, "Effect of on-chip ESD protection on 10 Gb/s receivers," EOS/ESD Symp. Proc., pp. 106-115, 2011.

N. Jack and E. Rosenbaum, "Voltage monitor circuit for ESD diagnosis," EOS/ESD Symp. Proc., pp. 370-378, 2011. (Outstanding Paper Award)

N. Olson, V. Shukla and E. Rosenbaum, "Test chip design for study of CDM related failures in SoC designs," Proc. Int. Rel. Phys. Symp., pp. EL.3.1-EL.3.6, 2011.

N. Jack, T. Maloney, B. Chou and E. Rosenbaum, "WCDM2-Wafer-level charged device model testing with high repeatability," Proc. Int. Rel.Phys. Symp., pp. 4C.5.1-4C.5.8, 2011.

J. Di Sarro and E. Rosenbaum, "A scalable SCR compact model for ESD circuit simulation," IEEE Trans. Elec. Dev., vol. 57, no. 12, pp. 3275-3286, 2010.

N. Jack, V. Shukla and E. Rosenbaum, "Investigation of current flow during wafer-level CDM using real-time probing," EOS/ESD Symp. Proc., pp. 389-397, 2010. (Best Student Paper Award)

V. Shukla and E. Rosenbaum, "CDM simulation study of a system-in-package," EOS/ESD Symp. Proc., pp. 41-47, 2010.

V. Shukla, N. Jack and E. Rosenbaum, "Predictive simulation of CDM events to study effects of package, substrate resistivity and placement of ESD protection circuits on reliability of integrated circuits," Proc. IEEE Int. Rel. Phys. Symp. pp. 485-492, 2010.

F. Farbiz and E. Rosenbaum, "Understanding transient latchup hazards and the impact of guard rings," Proc. IEEE Int. Rel. Phys. Symp., pp. 466-473, 2010.

N. Olson, G. Boselli, A. Salman and E. Rosenbaum, "A novel TCAD-based methodology to minimize the impact of parasitic structures on ESD performance," Proc. IEEE Int. Rel. Phys. Symp., pp. 474-479, 2010.

N. Jack and E. Rosenbaum, "ESD protection for high-speed receiver circuits," Proc. IEEE Int. Rel. Phys. Symp. pp. 835-840, 2010. (Best Poster Award)

D. Klokotov, V. Shukla, J. Schutt-Ainé, and E. Rosenbaum, "Application of the latency insertion method (LIM) to the modeling of CDM ESD events," Proc. IEEE Electronic Components Technology Conf., pp. 652-656, 2010.

E. Rosenbaum, H.-M. Bae, K. Bhatia and A. Faust, "Moving signals on and off chip," 2009 IEEE Custom Integrated Circuits Conference (invited paper).

J. Di Sarro, Y. Yang, K. Chatty, R. Gauthier, A. Ille, S. Mitra, J. Li. C. Russ, E. Rosenbaum and D. Ioannou, ""ESD time-domain characterization of high-k gate dielectric in a 32 nm bulk CMOS technology," Proc. EOS/ESD Symp., pp. 196-203, 2009. (Best Student Paper Award.)

N. Jack, J. Davis, M. Chaine, and E. Rosenbaum, "HBM Cross Power Domain Failure Due to Secondary Tester Pulse," 2009 EOS/ESD Symp.

K. Bhatia, N. Jack and E. Rosenbaum, "Layout optimization of ESD protection diodes for high-frequency I/Os," IEEE Trans. Device and Materials Reliability, vol. 9, no. 3, pp. 465-475, 2009.

F. Farbiz and E. Rosenbaum, "A new compact model for external latchup," Micro. Rel., vol. 49, pp. 1447-1454, 2009.

J. Di Sarro and E. Rosenbaum, "Oscillatory transmission line pulsing for characterization of device transient response," IEEE Elec. Dev. Lett., vol. 30, no. 2, pp. 168-170, 2009.

F. Farbiz and E. Rosenbaum, "Guard ring interactions and their effect on CMOS latchup resilience," IEEE Int. Electron Devices Meeting Tech. Dig., pp. 345-348, 2008.

K. K. Hsueh, S.-H. Ke, J. Lee and E. Rosenbaum, "UVeriESD: An ESD Verification Tool for SoC Design," 2008 IEEE Asia Pacific Conference on Circuits and Systems.

J. Lee and E. Rosenbaum, "Voltage clamping requirements for ESD protection of inputs in 90nm CMOS technology," Proc. EOS/ESD Symp., pp. 50-58, 2008.

J. Di Sarro, V. Vashchenko, E. Rosenbaum and P. Hopper, "A dual-base triggered SCR with very low leakage current and adjustable trigger voltage," Proc. EOS/ESD Symp., pp. 242-248, 2008.

N. Olson, V. Vashchenko, E. Rosenbaum and P. Hopper, "Small footprint trigger voltage control circuit for mixed-voltage applications," Proc. EOS/ESD Symp., pp. 196-203, 2008.

J. Di Sarro and E. Rosenbaum, "A scalable SCR compact model for ESD circuit simu lation," IEEE Int. Rel. Phys. Symp., pp. 254-261, 2008.

F. Farbiz and E. Rosenbaum, "Modeling of majority and minority carrier triggered external latchup," Proc. IEEE Int. Rel. Phys. Symp., pp. 270-277, 2008. (Best Student Paper Award)

K. Bhatia, S. Hyvonen and E. Rosenbaum, "A compact, ESD-protected, SiGe BiCMOS LNA for ultra-wideband applications," IEEE Journal of Solid-State Circuits, vol.42, no. 5, pp.1121-1130, 2007.

F. Farbiz and E. Rosenbaum, "An investigation of external latchup," Proc. IEEE Int. Rel. Phys. Symp, pp. 600-601, 2007.

J. Di Sarro, K. Chatty, R. Gauthier and E. Rosenbaum, "Evaluation of SCR-based ESD protection devices in 90nm and 65nm CMOS technologies," Proc. IEEE Int. Rel. Phys. Symp, pp. 348-357, 2007.

F. Farbiz and E. Rosenbaum, "Analytical modeling of external latchup," EOS/ESD Symp. Proc., pp. 338-346, 2007.

A. Gerdemann, K. Bhatia, E. Rosenbaum, "A Kelvin transmission line pulsing system with optimized oscilloscope ranging," EOS/ESD Symp. Proc., pp. 80-88, 2007.

K. Bhatia and E. Rosenbaum, "Layout guidelines for optimized ESD protection diodes," EOS/ESD Symp. Proc., pp. 19-27, 2007.

A. Gerdemann, E. Rosenbaum and M. Stockinger, "A novel testing approach for full-chip CDM characterization," EOS/ESD Symp. Proc., pp. 289-296, 2007.

J. Li, S. Joshi, R. Barnes and E. Rosenbaum, "Compact modeling of on-chip ESD protection devices using Verilog-A," IEEE Trans. CAD, vol. 25, no. 6, pp. 1047-1063, 2006.

H. Li, C. Zemke, G. Manetas, V. Okhmatovski, E. Rosenbaum and A. Cangellaris,"An automated and efficient substrate noise analysis tool,"IEEE Trans. CAD., vol. 25, no. 3, pp.454-468, 2006.

K. Bhatia, S. Hyvonen and E. Rosenbaum, "An 8-mW, ESD-protected, CMOS LNA for ultra-wideband applications," Proc. IEEE Custom Integrated Circuits Conf., pp. 385-388, 2006.

K. Bhatia, K. Kim, C.-T. Chuang, E. Rosenbaum, J.-O. Plouchart, and B. Floyd, "Double-gate FET technology for RF applications: device characteristics and low noise amplifier design," Proc. IEEE International SOI Conference, pp. 75-76, 2006.

J. Di Sarro, K. Chatty, R. Gauthier and E. Rosenbaum, "Study of design factors affecting the turn-on time of silicon controlled rectifiers (SCRs) in 90 and 65 nm bulk CMOS technologies," Proc. IEEE Int. Rel. Phys. Symp., pp. 163-168, 2006.

V. Chen, A. Salman, S. Beebe, E. Rosenbaum, S. Mitra, C. Putnam, R. Gauthier, "SOI poly-defined diode for ESD protection in high speed I/Os," Proc. IEEE Int. Rel. Phys. Symp., pp. 635-636, 2006.

S. Hyvonen, K. Bhatia and E. Rosenbaum, "An ESD-protected 2.45/5.25-GHz dual-band CMOS LNA with series LC loads and a 0.5-V supply," IEEE RFIC Symposium, pp. 43-46, 2005.

E. Rosenbaum and S. Hyvonen, "On-chip ESD protection for RF I/Os: devices, circuits and models," Proceedings International Symposium on Circuits and Systems, pp. 1202-1205, 2005.

S. Joshi, S. Hyvonen and E. Rosenbaum, "High-Q ESD protection devices for use at RF and broadband I/O pins," IEEE Trans. Elec. Dev., vol. 52, no. 7, pp. 1484-1488, 2005.

J. Li, H. Li, R. Barnes and E. Rosenbaum, "Comprehensive study of drain breakdown in MOSFETs," IEEE. Trans. Elec. Dev., vol. 52, no. 6, pp. 1180-1186, 2005.

S. Hyvonen and E. Rosenbaum, "Diode-based tuned ESD protection for 5.25-GHz CMOS LNAs," Proc. EOS/ESD Symposium, pp. 9-17, 2005.

S. Joshi, R. Ida and E. Rosenbaum, "Design and optimization of vertical SiGe thyristors for on-chip ESD protection," IEEE Trans. Device and Materials Reliability, vol. 4, no. 4, pp. 586-593, 2004.

J. Wu and E. Rosenbaum, "Gate oxide reliability under ESD-like pulse stress," IEEE Trans. on Electron Devices, vol. 51, no. 7, pp. 1192-1196, 2004. Paper was printed with incorrect art. Corrected version was published in no. 9, pp. 1528-1532.

R. Kanj and E. Rosenbaum, "A critical evaluation of SOI design guidelines," IEEE Trans. on VLSI Systems, vol. 12, no. 9, pp. 885-894, 2004.

S. Hyvonen, S. Joshi, and E. Rosenbaum, "Combined TLP/RF Testing System for Detection of ESD Failures in RF Circuits," IEEE Transactions on Electronics Packaging Manufacturing, vol. 28, no. 3, pp. 224-230, 2005.

S. Hyvonen, S. Joshi, and E. Rosenbaum, "Comprehensive ESD Protection for RF inputs," Micro. Rel., vol. 45, pp. 245-254, 2005.

J. Li, S. Hyvonen and E. Rosenbaum, "Improved wafer-level VFTLP system and investigation of device turn-on effects," Proc. EOS/ESD Symp., pp. 331-337, 2004.

J. Li, R. Gauthier and E. Rosenbaum, "A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection," Proc. EOS/ESD Symp., pp. 273-279, 2004.

R. Kanj, T. Lehner, B. Agrawal and E. Rosenbaum, "Noise characterization of static CMOS gates," Proc. of 41st IEEE/ACM Des. Automat. Conf , pp. 888-893, 2004.

S. Joshi and E. Rosenbaum, "ESD protection for broadband ICs (DC-20 GHz and beyond)," Elec. Lett., vol. 39, no. 12, pp. 906-908, 2003.

S. Joshi and E. Rosenbaum, "Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation," Micro. Rel., vol. 43, pp. 1021-1027, 2003.

J. Li, S. Joshi and E. Rosenbaum, "A Verilog-A compact model for ESD protection NMOSTs," Proc. IEEE Custom Integrated Circuits Conf., pp. 253-256, 2003.

S. Joshi, R. Ida and E. Rosenbaum, "A study of vertical SiGe thyristor design and optimization," Proc. EOS/ESD Symp., pp. pp. 224-232, 2003.

S. Hyvonen, S. Joshi and E. Rosenbaum, "Comprehensive ESD protection for RF Inputs," Proc. EOS/ESD Symp., pp. 188-194, 2003. (Best Student Paper Award)

S. Joshi and E. Rosenbaum, "Transmission line pulsed waveform shaping with microwave filters," Proc. EOS/ESD Symp., pp. 364-371, 2003.

S. Hyvonen, S. Joshi and E. Rosenbaum, "Combined TLP/RF testing system for detection of ESD failures in RF circuits," Proc. EOS/ESD Symp., pp. 346-353, 2003.

S. Hyvonen, S. Joshi and E. Rosenbaum, "A cancellation technique to provide ESD protection for multi-GHz RF inputs," Electronics Letters, vol. 39, no. 3, pp. 284-286, 2003.

H. Li, J. Carballido, H. Yu, V. Okhmatovski, E. Rosenbaum and A. Cangellaris, "Comprehensive frequency-dependent substrate noise analysis using boundary element methods," Proc. ICCAD, pp. 2-9, Nov. 2002.

R. Kanj, E. Rosenbaum and T. Lehner, "Bipolar leakage modeling for switch-level simulators," Proc. IEEE International SOI Conference, pp. 147-149, Oct. 2002.

S. Joshi and E. Rosenbaum, "Compact modeling of vertical ESD protection npn transistors for RF circuits," EOS/ESD Symposium, pp. 289-295, Oct. 2002.

R. Kanj and E. Rosenbaum, "A critical look at design guidelines for SOI logic gates," IEEE Int. Symp. on Circuits and Systems, vol. 3, pp. 261-264, 2002.

P. Juliano and E. Rosenbaum, "A novel SCR macromodel for ESD circuit simulation," Int. Electron Devices Meeting Tech. Dig., pp. 319-322, 2001.

P. Juliano and E. Rosenbaum, "Accurate wafer-level measurement of ESD protection device turn-on using a modified very fast transmission line pulse system," IEEE Trans. Device and Materials Reliability, vol.1, no. 2, pp. 95-103, 2001.

Y. Wang, P. Juliano, S. Joshi and E. Rosenbaum, "Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits," Micro. Rel., vol. 41, no. 11, pp. 1781-1787, 2001.

J. Wu, P. Juliano, E. Rosenbaum, "Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions," Micro. Rel., vol. 41, no. 11, pp. 1771-1779, 2001.

R. Kanj and E. Rosenbaum, "Multiple output domino logic (MODL) in SOI," Proc. IEEE Int. SOI Conf., pp. 59-60, 2001.

E. Li, E. Rosenbaum, J. Tao and P. Fang "Projecting lifetime of deep submicron MOSFETs," IEEE Trans. Elec. Dev., vol. 48, no.4, pp. 671-678, 2001.

S. Joshi, R. Ida, P. Givelin and E. Rosenbaum, "An analysis of bipolar breakdown and its application to the design of ESD protection circuits," Proc. Int. Rel. Phys. Symp., pp. 240-245, 2001.

E. Rosenbaum and J. Wu, "Trap generation and breakdown processes in very thin gate oxides," Microelectronics Reliability, vol. 41, no. 5, pp. 625-632, 2001. (Invited Paper)

Y. Wang, P. Juliano, S. Joshi and E. Rosenbaum, "Electrothermal modeling of ESD diodes in bulk-Si and SOI technologies," Proc. EOS/ESD Symp., pp. 430-436, 2000.

J. Wu, P. Juliano and E. Rosenbaum, "Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions, Proc. EOS/ESD Symp., pp. 287-295, 2000.

S. Voldman, P. Juliano, N. Schmidt, R. Johnson, L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, D. Harame, E. Rosenbaum and B. Meyerson, "Electrostatic discharge characterization of epitaxial-base silicon-germanium heterojunction bipolar transistors," Proc. EOS/ESD Symp., pp. 239-250, 2000.

S. Joshi, P. Juliano, E. Rosenbaum, G. Kaatz and S. M. Kang, "ESD protection for BiCMOS circuits," Proc. Bipolar/BiCMOS Circuits and Tech. Mtg., pp. 218-221, 2000.

E. Rosenbaum and J. Wu, "Present understanding of gate oxide wearout," Proc. European Solid-State Device Research Conf., pp.54-59, 2000.

E. Li, E. Rosenbaum, L. F. Register, J. Tao and P. Fang, "Hot carrier induced degradation in deep submicron MOSFETs at 100 C," Proc. Intl. Rel. Phys. Symp., pp. 103-107, 2000.

J. Wu, E. Rosenbaum, B. MacDonald, E. Li, J. Tao, B. Tracy and P. Fang, "Anode hole injection versus hydrogen release: the mechanism for gate oxide breakdown," Proc. Intl. Rel. Phys. Symp., 27-32, 2000.

S. Voldman, P. Juliano, R. Johnson, N. Schmidt, A. Joseph, S. Furkay, E. Rosenbaum, J. Dunn, D. Harame and B. Meyerson, "Electrostatic discharge and high current pulse characterization of epitaxial-base Silicon-Germanium heterojunction bipolar transistors," Proc. Intl. Rel. Phys. Symp., pp. 310-316, 2000.

D. Chen, E. Li, E. Rosenbaum and S. M. Kang, "Interconnect Thermal Modeling for Accurate Simulation of Circuit Timing and Reliability," IEEE Trans. CAD IC and Syst, vol. 19, no. 2, pp. 197-205, 2000.

D. Chen, E. Li, E. Rosenbaum and S. M. Kang, "Interconnect thermal modeling for determining design limits on current density," Int. Symp. on Physical Design, p. 172, 1999.

E. Li, E. Rosenbaum, J. Tao, G. Yeap, M.-R. Lin and P. Fang, "Hot carrier effects in nMOSFETS in 0.1um CMOS technology," Intl. Rel. Phys. Symp, p. 253, 1999.

J. Wu, L. F. Register, and E. Rosenbaum, "Trap assisted tunneling current through ultra-thin oxide," Intl. Rel. Phys. Symp, p. 389, 1999.

P. Raha, C. Diaz, E. Rosenbaum, M. Cao, P. VandeVoorde, and W. Greene, "EOS/ESD reliability of partially-depleted SOI technology," IEEE Trans. on Electron Devices, vol. 46, no. 2, p. 429, 1999.

L. F. Register, E. Rosenbaum and K. Yang, "Analytic model for direct tunneling current in polycrystalline silicon-gate metal-oxide-semiconductor devices," Applied Physics Letters, vol. 74, no. 3, p. 457, 1999.

P. Raha, J. Smith, J. Miller and E. Rosenbaum, "ESD robustness prediction and protection device design in partially-depleted SOI technology," Microelectronics Rel. J., vol. 38, no. 11, p. 1723, 1998.

Y.-K. Cheng, P. Raha, C.-C. Teng, E. Rosenbaum and S. M. Kang, "ILLIADS-T: An electrothermal timing simulator for temperature profiling of VLSI chips," IEEE Trans. on CAD of Ckts. and Syst., vol. 17, no. 8, pp. 668-681, 1998.

E. Li, E. Rosenbaum, J. Tao and P. Fang, "CMOS hot carrier lifetime improvement from deuterium anneal," Device Research Conf., pp. 22-23, 1998.

T. Li, C.-H. Tsai, E. Rosenbaum and S,-M. Kang, "Substrate resistance modeling and circuit-level simulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress," EOS/ESD Symp. Proc., pp. 281-289, 1998.

T. Li, C.-H. Tsai, E. Rosenbaum and S.-M. Kang, "Modeling, extraction and simulation of CMOS I/O circuits under ESD stress," IEEE Int'l Symposium on Circuits and Systems, pp. 389-392, 1998.

T. Li, P. Bendix, D. Suh, Y. J. Huh, E. Rosenbaum, A. Kapoor and S. M. Kang, "Optimum Design for a Two-Stage CMOS I/O ESD Protection Circuit," IEEE IEEE International Symposium on Circuits and Systems, pp. 113-116, 1998.

C.-C. Teng, Y.-K. Cheng, E. Rosenbaum and S. M. Kang, "iTEM: A temperature dependent electromigration reliability diagnosis tool,"IEEE Trans. on CAD of Int. Ckts. and Syst., vol. 16, no. 8, pp. 882-894.

P. Raha, J. Miller and E. Rosenbaum, "Time-dependent snapback in thin film SOI MOSFETs, IEEE Electron Device Letters, vol. 18, no. 11, p.509, 1997.

P. Raha, J. Smith, J. Miller and E. Rosenbaum, "Prediction of ESD protection levels and novel protection devices in thin film SOI technology," 1997 EOS/ESD Symposium Proc., p. 356, 1997.

T. Li, D. Suh, S. Ramaswamy, P. Bendix, E. Rosenbaum, A. Kapoor, and S. M. Kang, "Study of a deep-submicron I/O protection circuit using circuit-level simulation," Int. Reliability Physics Symp. Proc., p. 333, 1997.

T. Li, S. Ramaswamy, E. Rosenbaum and S. M. Kang, "Circuit-level simulation and layout optimization for deep submicron EOS/ESD output protection device," IEEE Custom Integrated Circuits Conf., p. 159, 1997.

P. Raha, S. Ramaswamy and E. Rosenbaum, "Heat flow analysis for EOS/ESD protection device design in SOI technology," IEEE Trans. on Electron Devices, vol. 44, no. 3, p. 464, 1997.

E. Rosenbaum and L. F. Register, "Mechanism of stress-induced leakage current in MOS capacitors," IEEE Trans. on Electron Devices, vol. 44, no. 2, p. 317, 1997.

E. Rosenbaum, J. King and C. Hu, "Accelerated testing of SiO2 reliability," IEEE Trans. on Electron Devices, vol. 43, no. 1, p. 70, January 1996.

C. Teng, Y. Cheng, E. Rosenbaum and S. Kang, "iTEM: A chip-level electromigration reliability diagnosis tool using electrothermal timing simulation," Int. Reliability Physics Symp. Proc., p. 172, 1996.

Y. Cheng, C. Teng, A. Dharchoudhury, E. Rosenbaum and S. Kang, "iCET: A complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips," 33rd Design Automation Conference, p. 548, 1996.

C. Teng, Y. Cheng, E. Rosenbaum and S. Kang, "Hierarchical electromigration reliability diagnosis for VLSI interconnects," 33rd Design Automation Conf., p. 752, 1996.

S. Ramaswamy, E. Li, E. Rosenbaum and S. Kang, "Circuit-level simulation of CDM-ESD and EOS in submicron MOS devices," EOS/ESD Symp. Proc., p. 316, 1996.

Y. Cheng, C. Teng, A. Dharchoudhury, E. Rosenbaum and S. Kang, "Improvement on chip-level electrothermal simulator - ILLIADS-T," Proc. ISCAS, p. 432, 1996.

Y. Cheng, C. Teng, A. Dharchoudhury, E. Rosenbaum and S. Kang, "A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips," Proc. ISCAS, p. 580, 1996.

S. Ramaswamy, P. Raha, E. Rosenbaum and S. Kang, "EOS/ESD protection circuit design for deep submicron SOI technology," EOS/ESD Symp. Proc., p. 212, 1995.

E. Minami, S. Kuusinen, E. Rosenbaum, P. Ko and C. Hu, "Circuit-level simulation of TDDB failure in digital CMOS circuits," IEEE Trans. on Semiconductor Manufacturing, vol. 8, no. 3, p. 370, 1995.

C. Felsch and E. Rosenbaum, "The relation between oxide degradation and oxide breakdown," Int. Reliability Physics Symp. Proc., p. 142, 1995.

W. Sun, E. Rosenbaum and S. Kang, "Fast timing simulation for submicron hot-carrier degradation," Int. Reliability Physics Symp. Proc., p. 65, 1995.

E. Rosenbaum, Z. Liu and C. Hu, "Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions," IEEE Trans. on Electron Devices, vol. 40, no. 12, p. 2287, 1993.

K. Quader, C. Li, R. Tu, E. Rosenbaum, P. Ko and C. Hu, "A bi-directional NMOSFET current reduction model for simulation of hot- carrier-induced circuit degradation," IEEE Trans. on Electron Devices, vol. 40, no. 12, p. 337, 1993.

R. Tu, E. Rosenbaum, W. Chan, C. Li, E. Minami, K. Quader, P. Ko and C. Hu, "Berkeley reliability tools - BERT," IEEE Trans. on CAD of Integrated Circuits and Systems, vol. 12, no. 10, 1993.

E. Rosenbaum, Z. Liu and C. Hu, "The effects of oxide stress waveform on MOSFET performance," Int. Electron Devices Mtg. Tech. Dig., p. 719, 1991.

Z. Liu, E. Rosenbaum, P. Ko, C. Hu, Y. Cheng, C. Sodini, J. Gross and T. Ma, "A comparative study of the effects of dynamic stressing on high-field endurance of reoxidized-nitrided, fluorinated and conventional oxides," Int. Electron Devices Mtg. Tech. Dig., p. 723, 1991.

K. Quader, C. Li, R. Tu, E. Rosenbaum, P. Ko and C. Hu, "A new approach for simulation of circuit degradation due to hot-electron damage in NMOSFETs," Int. Electron Devices Mtg. Tech. Dig., p. 337, 1991.

E. Rosenbaum, R. Rofan and C. Hu, "Effect of hot-carrier injection on n- and pMOSFET gate oxide integrity," IEEE Electron Device Ltr., vol. 12, no. 11, p. 599, 1991.

E. Rosenbaum and C. Hu, "High-frequency time-dependent breakdown of SiO2," IEEE Electron Device Ltr., vol. 12, no. 6, p. 267, 1991. (Best Student Paper Award)

E. Rosenbaum, R. Moazzami and C. Hu, "Implications of waveform and thickness dependence of SiO2 breakdown on accelerated testing," Proc. of the Int. Symp. on VLSI Tech., Systems, and Applications, p. 214, 1991.

E. Rosenbaum, P. Lee, R. Moazzami, P. Ko and C. Hu, "Circuit reliability simulator - oxide breakdown module," Int. Electron Devices Mtg. Tech. Dig., p. 331, 1989.